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| 等 级：资深长老 |
| 经 验 值：1583 |
| 魅 力 值：699 |
| 龙 币：6623 |
| 积 分：2969.6 |
| 注册日期：2002-06-30 |
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AMD职位：Senior ASIC Engineer for Chip Integration
有感兴趣的联系我：18601272860，米先生
Job Description: Responsibility:
• Integrate functional IPs into SoC per architectural requirement.
• Develop RTL code for macro blocks in Verilog HDL and make sure functional correct and reusable for different configuration.
• Participate in making functional/technology based chip targets in timing, area, power. Develop timing constraint, power intent spec accordingly.
• Synthesis and deliver qualified netlist, cowork with PD to settle chip floorplan and achieve timing closure.
Requirement:
• Major in EE, CS or related, Master Degree with 3+ years or Bachelor with 5+ years working experiences in ASIC Company.
• familiar with one or more ASIC flows (logic synthesis, STA, formality check, Design for Power ) and usage of related EDA tools.
• Familiar with script languages((tcl, perl etc.) in unix/linux.
• Good written and spoken English.
• Good communication skills and be able to work both independently and in a team.
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2011-12-13 10:48:47
