 |
| 等 级：长老 |
| 经 验 值：1778 |
| 魅 力 值：218 |
| 龙 币：1658 |
| 积 分：1317.6 |
| 注册日期：2002-09-29 |
| |
|
|
|
关于RISC/CISC，这里有篇文章，可以和你的BUAA BOOK佐着看看，
http://arstechnica.com/cpu/4q99/risc-cisc/rvc-1.html
At this point, I抎 like to reference a statement made by David Ditzel, the chief architect of Sun抯 SPARC family and CEO of Transmeta.
"Today [in RISC] we have large design teams and long design cycles," he said. "The performance story is also much less clear now. The die sizes are no longer small. It just doesn't seem to make as much sense." The result is the current crop of complex RISC chips. "Superscalar and out-of-order execution are the biggest problem areas that have impeded performance [leaps]," Ditzel said. "The MIPS R10,000 and HP PA-8000 seem much more complex to me than today's standard CISC architecture, which is the Pentium II. So where is the advantage of RISC, if the chips aren't as simple anymore?"
|
| |
|
|
2004-11-19 12:32:20
